The present invention relates to a method and apparatus for carrying out debugging procedures on a processor, for example a microprocessor or Digital Signal Processing (DSP) processor.
Software debugging is commonly carried out using In Circuit Emulation (ICE) wherein a monitor program located in the microprocessor provides information to an external host.
It has been recognised that software debugging using ICE techniques may be carried out more expeditiously using techniques adapted from production testing of microprocessors with production scan-chains. Such production scan chains are to be distinguished from boundary scan registers as in the known JTAG standards. In production scan chains, registers are provided throughout the processor so that the working of a software routine throughout the processor can be observed, i.e. it is xe2x80x9cvisiblexe2x80x9d. Such production scan chain of registers can be loaded with a random pattern of logic values. One or more machine cycles may then be executed, and the logic values are fed into the microprocessor logic. The resultant logic values in the registers may then be uploaded and examined to assess whether the microprocessor logic is working correctly.
Referring now to FIG. 1 of the drawings, this shows a block diagram of a previously proposed technique for using an existing production test scan-chain in a microprocessor for software debugging. As shown in FIG. 1, a pipelined microprocessor 2 is coupled via an Address Bus 4 and Data Bus 6 to a program RAM 8. The Address Bus 4 is also coupled to a Breakpoint Detect Unit 10. A clock controller 12 is provided and a Scan Controller 14 external to the microprocessor controls the operation of the scan mode.
A chain of internal scan registers 16 is such that the state of the microprocessor is completely described in the registers. Further the registers may be accessed during normal operation of the microprocessor.
The method of software debug using a production scan-chain is referred to herein as Scan In-Circuit Emulation (ScanICE). ScanICE mode is entered whenever access is required to the internal processor state, such as on reaching a software breakpoint. FIG. 1 illustrates a previous approach to entering ScanICE mode where only breakpoints on program addresses are considered. A register in the Breakpoint Detect Unit 10 is initialised to the required breakpoint address. When a match occurs between the Program Address Bus 4 and this register, an Enter ScanICE signal on a line 18 is asserted. This triggers the Clock Controller 12 to halt appropriate clocks so that the off-chip Scan Controller 14 can initiate scanning. The Scan Controller 14 uses the Scan Enable and Test signals to configure registers in the scan-chain 16 to shift serially when clocked and supplies the Scan Clock.
Using the scanned-but data for observability and scanned-in data for controllability the controller 14 can provide all required facilities for debugging software running on the microprocessor. When ScanICE functions are complete, Leave Scan is asserted on a line 20 forcing the Clock Controller to restart clocks and resume normal operation. The approach of FIG. 1 for entering ScanICE mode suffers from a number of problems:
1. To ease software development it is often required that the microprocessor""s pipeline is hidden from the programmer. This means that all registers""contents refer to the same instruction. In a processor with, for example, a data pipeline, simply stopping the clock will result in several instructions being in varying states of execution. This is illustrated in FIG. 2 for a simple multiplier data path. The pipeline is used to separate the operation of reading from memory and actually multiplying so that they can be carried out in parallel using the X and Y registers 22,24 as a temporary store (which are part of the production scan chain). For successive single-cycle multiply instructions, two instructions are being executed at any one time; the result of one is loaded into the product register 26 on a particular clock-edge and the data operands of the next are loaded into the X and Y registers 22,24. By simply stopping the clock the Host debugger will have great difficulty in separating the instructions with just the knowledge of what is held in the X, Y and Product registers.
2. It is often required that a processor be able to access slow-memory without using a very slow clock. One way of achieving this is to provide a wait-state mechanism whereby the processor is halted during the memory access. This is illustrated in FIG. 3. Following an access to a slow memory 30, a Memory Interface Unit 32 asserts a Wait signal and Clock Controller 12 stops the clock to the Microprocessor 2. Following a defined number of clocks of the Memory Interface Unit 32 (as monitored by a counter 34) the Wait signal is released and the clock to the Microprocessor is started again and normal operation resumes. When a breakpoint is detected, the Clock Controller must detect the fact that an access to slow memory is occurring and continue clocking the Memory Interface Unit to complete the access before stopping all clocks. This is an undesirable complication.
Depending on the functionality of the microprocessor, there are many other scenarios when just stopping the main clock and entering ScanICE may cause problems. These problems get more numerous as pipelines get more complex and more elaborate schemes are implemented for improving microprocessor performance.
The present invention provides apparatus for carrying out debugging procedures on a processor, the processor including a production scan chain of scan registers, scan interface means for interfacing with a scan controller means external of the processor, a breakpoint interrupt means for executing an interrupt instruction and a processor clock control means, wherein, when in the operation of the processor a breakpoint is detected or generated, the breakpoint interrupt means executes an interrupt, the processor completes its current instruction and then branches to a Interrupt Service Vector, completion of which is signalled to the scan interface means which provides a Start Scan signal to the clock control means, following""which the scan interface means signals the external scan controller to begin a scanning operation.
In a further aspect, the present invention provides a method for carrying out debugging procedures on a processor, the method comprising the following steps:
1) providing a processor with a production scan chain of scan registers, a scan interface means for interfacing with an external scan controller means, a breakpoint interrupt means for executing an interrupt instruction, and a processor clock control means;
2) detecting or generating a breakpoint in the operation of the processor;
3) the breakpoint interrupt means executes an interrupt instruction as a result of which the processor completes its current instruction, and signals the same to the scan interface means;
4) the scan interface means asserts a Start Scan signal to the processor clock control means, which whereupon stops the processor clock or clocks; and
5) the external scan controller means is alerted to start a scan sequence.
In accordance with, the invention, an improved technique is provided for entering an In Circuit Emulation session which avoids problems experienced in stopping the microprocessor clock without upsetting current actions of the microprocessor, and in recovering information of pipelined instructions.
Preferably, in the operation of the invention, after the microprocessor has completed its current instructions, the microprocessor pipeline is filled with no operation (NOP) instructions.
The present invention is particularly applicable to pipelined processors, especially DSP processor cores.